Ferroelectric substances may be used as dielectric layer materials in ferroelectric capacitors that are integrated in semiconductor memory devices. The ferroelectric substance exhibits voluntary polarization throughout a range of temperatures without an external electric field. Moreover, if a reverse electric field is applied to the ferroelectric substance, its polarized state can be inverted from one direction to an opposite direction. The ferroelectric substance has hysteresis characteristics according to the direction and size of the applied electric field. Ferroelectric random access memory (FRAM) devices utilize the hysteresis characteristics of the ferroelectric substance to achieve non-volatile performance characteristics.
A difficult problem associated with the manufacture of a ferroelectric capacitor has been the infiltration of hydrogen into ferroelectric materials during various etching processes and insulation layer forming processes. This infiltration of hydrogen can deteriorate the hysteresis characteristics of the ferroelectric material within the capacitor and degrade its non-volatile performance.
FIGS. 1 and 2 are cross-sectional views illustrating a conventional method of manufacturing a ferroelectric capacitor of a semiconductor device. Referring to FIG. 1, a first metal layer 40 (for a lower electrode layer of a ferroelectric capacitor) is formed on a lower interlayer dielectric layer 20 placed on a semiconductor substrate 10. The first metal layer 40 is connected to an impurity region in the semiconductor substrate via a contact plug 30 that penetrates the lower interlayer dielectric layer 20. Next, a ferroelectric layer and a second metal layer are sequentially formed on the first metal layer 40. The second metal layer is used for forming an upper electrode layer. The second metal layer and the ferroelectric layer are sequentially patterned to form a second metal layer pattern 60 and a ferroelectric layer pattern 50. Next, an oxide layer 70 is formed so as to be used as an etching mask in patterning the first metal layer 40. Conventionally, a phosphosilicate glass (PSG) layer is used as the oxide layer 70. Alternatively, a titanium nitride (TiN) layer may be used instead of the oxide layer 70.
Referring to FIG. 2, a first metal layer pattern 45 is formed by partially removing the first metal layer 40 using the oxide layer 70 as an etching mask. Next, a barrier layer 80 covering the first metal layer pattern 45 and the oxide layer 70 is formed. A TiO2 layer 81 and an Al2O3 layer 82 may be used as the barrier layer 80. In some cases, only the TiO2 layer 81 is used. Next, an upper interlayer dielectric layer 90 is formed on the barrier layer 80.
In the method for manufacturing a ferroelectric capacitor as described above, the oxide layer 70, having a relatively low hydrogen content, is used as an etching mask and the barrier layer 80, which includes a TiO2 layer 81 and an Al2O3 layer 82, is formed before formation of the upper interlayer dielectric layer 90. The oxide layer 70 and the barrier layer 80 operate to inhibit the characteristics of the ferroelectric layer pattern 50 from deteriorating due to penetration of hydrogen. However, because the oxide layer 70 may contain some hydrogen, hydrogen may infiltrate into the ferroelectric layer pattern 50. Also, there are frequently problems associated with the formation of the barrier layer 80. For example, in the event the TiO2 layer 81 is used alone, a high temperature thermal treatment process is typically required for enhancing the dielectric characteristics of the layer. During the thermal treatment process, however, a metal barrier layer (not shown) placed between the first metal layer pattern 40 and the underlying contact plug 30 may be oxidized and the contact resistance of the contact plug 30 may increase. To inhibit the increase in contact resistance, a dual layer consisting of the TiO2 layer 81 and the Al2O3 layer 82 should be used as the barrier layer 80 and in this case, a low temperature thermal treatment process may be performed on the barrier layer 80 after the TiO2 layer 81 is formed. However, in a step for forming a via hole in a peripheral circuit region, which is typically performed after formation of a ferroelectric capacitor, the size of the via hole may be reduced due to a difference in etching selectivity between the barrier layer 80 and an adjacent dielectric layer (not shown). Accordingly, the contact resistance in the peripheral circuit region may increase. To solve this problem, an additional process for removing the barrier layer 80 in the peripheral circuit region, particularly, the TiO2 layer 81, typically must be performed.